Design of Framework for Logic Synthesis Engine

Logic synthesis is a novel architectural concept used for converting a high level description of logic circuit into optimized gate level description. The method ranges from transforming a RTL description to producing an optimized netlist. Logic minimization plays an important role in optimization of logic synthesis. This optimization is done through the function minimization through different existing methods. The existing work on function minimization has resulted into many algorithms. In the proposed work, we form the basis for our synthesis engines vide detailed performance analysis and insight into the various minimization algorithms proposed erstwhile, and apply them on some real example circuit. We plan to propose our own algorithm as well for enhanced performance.